This invention relates generally to the layout of a semiconductor chip. In particular, the invention relates to a method of arranging the components of a logic stage so as to align the outputs of one stage with the inputs of another stage.
A popular type of logic circuit suited for implementation in MOSFET (metal-oxide-semiconductor field-effect transister) technology is described by Weinberger in a technical article entitled "Large Scale Integration of MOS Complex Logic: A Layout Method" and appearing in IEEE Journal of Solid-State Circuits, Vol. SC-2, No. 4, December 1967 at pages 182-190. An illustrative example of a gate-level representation of a logic circuit of this logic is shown in FIG. 1. A load transistor 10 is connected in series with a logic group 12 between a fixed power supply voltage V.sub.DD and ground. The connection between the load transistor 10 and the logic group 12 is connected to the output V.sub.out of this stage of the logic. Within the logic group 12 is a configuration of logic transistors 14, each gate of which is controlled by a logic output V.sub.out of a another logic circuit or possibly one of the inputs to the chip. The number and arrangement of the logic transistors 14 determine which logic function is performed by the logic group 12. The values of the signals applied to the gates of the logic transistors 14 control the output V.sub.out. If the input signals cause a conduction path to ground through the logic group 12, then the output V.sub.out is at ground potential. If no conduction path is created, then the output V.sub.out is at the power supply potential V.sub.DD. Only a single logic stage is represented in FIG. 1. In a typical logic chip, there would be very many logic circuits, with the outputs V.sub.out of some circuits controlling the gates of the logic transistors 14 of other circuits.
An efficient and compact semiconductor layout for parts of the circuit of FIG. 1 is shown in FIG. 2. A low resistivity semiconductor substrate is first covered with a thick oxide. Thereafter, the thick oxide is selectively removed to expose areas for a diffusion well 16. A thin oxide is then grown to form a gate insulating oxide in selected regions. Polysilicon lines are formed which cross the diffusion well 16 in the area of the thin gate oxide to define gate electrodes 18. Then the chip is uniformly subjected to ion implantation to create a higher semiconductor resistivity in portions of the surface of the semiconductor covered neither by the thick oxide nor the polysilicon lines, that is, to form and activate the diffusion well 16. The term diffusion well is a misnomer because the diffusion well 16 of FIG. 2 is not, in this case, formed by diffusion and is not a continuous well but is interrupted by the gate electrodes 18. Nonetheless, the terminology is common and will continue to be used. After an insulating oxide is grown or deposited, at least two metal lines 20 and 22, called the first metallization, are deposited transversely to the polysilicon electrodes 18 across the diffusion well 16. However, prior to the deposition of the metal lines 20 and 22, two contact holes 24 and 26 are formed through the intervening oxide in order that the metal lines 20 and 22 are connected to the diffusion well 16 at selected points. One metal line 20 is connected to the output voltage V.sub.out and the other metal line 22 is connected to ground. The polysilicon gate electrodes 18 are separately connected to input lines controlling the gates of the logic transistors 14. The layout of FIG. 2 produces the logic configuration shown in FIG. 3 which is a two-input NAND gate. Obviously, a higher order NAND gate could be produced by including more gate electrodes 18 between the two contact holes 24 and 26.
An alternative configuration is shown in FIG. 4, which is identical to FIG. 2 except for the locations of contact holes 28, 30 and 32, which alternate between the output voltage V.sub.out and ground. The layout of FIG. 4 produces the logic circuit shown in FIG. 5 which is a two-input NOR gate. Obviously again, a higher order NOR gate could be produced by including more gate electrodes 18 and more alternating contact holes 28-32.
The load transistor 10 can be easily implemented as shown in FIG. 6. A C-shaped diffusion well 34 is formed with a polysilicon gate electrode 36 crossing both arms of the diffusion well 34. The use of polysilicon gate electrodes in a Weinberger array is described by Cook et al in a technical article entitled "Polysilicon Gate MOSFETs for Weinberger-Type Random Logic Arrays" appearing the the IBM Technical Disclosure Bulletin, Vol. 19, No. 6, November 1976 at pages 2303-2304. A contact hole 38 connects the gate electrode 36 with the diffusion well 34 through the intervening oxide. The power supply V.sub.DD is connected to the free end of the arm of the diffusion well 34 other than that having the contact hole 38. The output voltage V.sub.out can be connected either to the gate electrode 38 or to the common side 40 of the diffusion well 34.
From the above discussion, it is apparent that a complete logic circuit illustrated in FIG. 1 can neatly be arranged in a vertical column with a single diffusion well. As a result, a logic chip can be built as a series of logic circuits, each having a particular logic function and with a single output of one circuit being used as one of several inputs of other logic circuits 44. Generally, the circuits are ordered in sequential stages with signals flowing from one side of a chip to the other.
One difficulty with the usual circuit arrangement on a chip lies in the interconnections between the circuits. An example of the difficulty is shown in FIG. 7 which shows the outputs of eight logic circuits 46 being combined in another logic circuit 48 which provides an 8-way NOR function. Eight interconnections 50 are required between the eight circuits 46 and the NOR circuit 48. A substantial length of the interconnections is vertically arranged in parallel between the circuits 46 and 48. Such a large number of vertical portions require that the circuits 46 and 48 be widely separated to accommodate the vertical portions, thus decreasing the packing density of the chip.